Wiring structure of printed wiring board and method for manufacturing the same

ABSTRACT

Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch. 
     In a semiconductor-embedded substrate, a conductive pattern is formed on both sides of a core substrate and a semiconductor device is placed in a resin layer stacked over the core substrate. The resin layer has via-holes so that the conductive pattern and a bump of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

BACKGROUND OF THE INVENTION

The present invention relates to a wiring structure in a multilayerprinted wiring board or component-embedded printed wiring board.

Multilayer printed wiring boards obtained by alternately stacking aninsulating layer and a wiring layer and component-embedded printedwiring boards having an insulating layer with electroniccomponent-embedded therein are known as a high density packagingstructure of electronic components such as semiconductor IC chips. Inprinted wiring boards having such a structure, as a method forconnecting a wiring layer to a body to be wired thereto such as anunderlying wiring layer or an electrode of an embedded electroniccomponent arranged below or inside the insulating layer, a method forforming, in the insulating layer, a connection hole which is called“via-hole” to expose therefrom the body to be wired and connecting thebody to be wired and the wiring layer inside the via-hole (refer toJapanese Patent Laid-Open Nos. 2006-100773 and 2005-64470) is known.

For the manufacture of wiring structure, three processes are generallyknown. They are an additive process of selectively forming a wiringlayer at a wiring pattern portion; a semi-additive process of forming abackground layer over the entire surface of a substrate, selectivelyremoving or masking a portion of the background layer other than thewiring pattern portion, and forming a wiring layer on the backgroundlayer which has remained or is exposed in the pattern form; and asubtractive process of forming a conductor layer over the entire surfaceof a substrate and then selectively removing a portion of the conductorlayer other than a wiring pattern portion to form a wiring layer. Thesemanufacturing processes of wiring structure are also employed commonlyfor the via-hole connection, that is, connection of a wiring layer and abody to be wired in a via-hole.

For example, there is disclosed in Japanese Patent Laid-Open No.2006-100773 a process (subtractive process) of forming, in a multilayerprinted wiring board, a conductor layer over the entire surface of asubstrate including the inner wall of a via-hole, and selectivelyremoving a portion of the conductor layer other than a wiring patternportion by photolithography and etching to form the wiring pattern.

In Japanese Patent Laid-Open No. 2005-64470, there is disclosed aprocess (semi-additive process) of forming, in a component-embeddedprinted wiring board, an underlying conductive layer over the entiresurface of a substrate including the inner wall of a via-hole, masking aportion of the underlying conductive layer other than a wiring patternportion and carrying out electroplating with the exposed underlyingconductive layer as a base to form the wiring pattern.

SUMMARY OF THE INVENTION

In either of the above-described manufacturing processes of wiringstructure, misalignment may occur when a wiring layer is patterned. Inorder to allow such misalignment and ensure the connection of a wiringlayer, a wiring structure in which the wiring layer is caused to extendfrom the outside of the upper portion of a via-hole to the surface of aninsulating layer tends to be employed. This means that as illustrated inFIGS. 15A and 15B, in the conventional via-hole connection, there is atendency to design it so as to make the width w of a wiring layer 153formed on a via-hole 150 greater than an opening diameter r of thevia-hole 150.

In this case, an insulation distance z between two adjacent wiringlayers is, as illustrated in these drawings, the shortest distancebetween sites of them extending on the surface of the insulating layer.It is inevitable to widen the distance of two adjacent via-holes(via-hole pitch) to some extent in order to secure this insulationdistance z sufficiently. Since a decrease in the arrangement distance ofbodies to be wired needs a decrease in the via-hole pitch, high densitypackaging of a printed wiring board cannot be realized freely under thepresent situation.

For realizing high-density packaging, it is presumed to be effective todecrease the width of a wire itself and arrange wiring patterns at anarrow pitch, thereby ensuring a distance between wires (insulationdistance). There is however a fear of failing to ensure completeconnection of a wire and a body to be wired when misalignment occurstherebetween. Such a failure in connection leads to problems such asdisconnection due to insufficient connection strength and an increase inthe connection resistance to an undesirable level.

With the foregoing in view, the present invention has been made. Anobject of the present invention is to provide a wiring structure capableof ensuring the connection between a wiring layer and a body to be wiredwhile maintaining insulation between two adjacent wiring layers, therebyachieving pitch reduction for high density packaging; and amanufacturing process thereof.

The present inventors have carried out an extensive investigation on thewiring structure of a via-hole connection. As a result, it has beenfound that the above-described object can be accomplished by forming,inside a connection hole in which a wiring layer and a body to be wiredare connected, a structure in which the wiring layer widens toward thebody to be wired, leading to the completion of the invention.

Described specifically, the wiring structure according to the presentinvention has an insulating layer having a connection hole formedtherein, a body to be wired which is disposed on the bottom of theconnection hole so as to expose at least a portion thereof, and a wiringlayer connected to the body to be wired inside the connection hole. Thewiring layer includes a portion whose cross-sectional area increasestoward the body to be wired and at the same time, it is located so as todefine a space region (void) between at least a portion of the innerwall of the connection hole and the wiring layer where they are not incontact.

The term “insulating layer” as used herein means a layer made of anelectrically insulating material and it embraces, for example, aninterlayer insulating layer in a multilayer printed wiring board or acomponent-embedded layer in a component-embedded printed wiring board.The term “body to be wired” means a subject body which is connected by awiring layer, in other words, a body to be wired to a wire and itembraces, for example, an underlying wiring layer in a multilayerprinted wiring board or an electrode of an embedded electronic componentin a component-embedded printed wiring board. The term “wiring layer”means a layer constituting a wiring pattern for electrically connectingthe body to be wired to another component mounted on a printed wiringboard. The term “cross-sectional area” of the wiring layer means across-sectional area of it on a plane parallel to a plane defined by theopening ends of a connection hole. The term “inner wall” of theconnection hole means a sidewall when the connection hole has, forexample, a cup-like shape (cylindrical shape having one closed end)whose wall can be clearly divided into a side wall and a bottom wall,while it means “a wall portion other than a portion corresponding to thebottom portion” when the connection hole has a shape whose wall cannotbe clearly divided into a side wall and a bottom wall.

In such a constitution, the wiring structure is formed by connecting thewiring layer to the body to be wired which is exposed from the bottom ofa connection hole formed in the insulating layer. Inside the connectionhole, the wiring layer has a portion whose cross-sectional area (whichmay be either a volume or cross-sectional width) increases graduallytoward the body to be wired and a space region in which the inner wallof the connection hole and the wiring layer are not in contact isdefined therebetween. In short, a wiring layer having a portion (forexample, a portion like a mountain, trapezoid or pyramid with theproviso that the side wall surface thereof is not required to be flat)widening toward the bottom of the connection hole, in other words,having a portion tapered toward the opening ends of the connection holeis formed and a void is defined between the side wall of the wiringlayer and the inner wall of the connection hole.

When connection holes which are adjacent to each other are formed andwiring layers having the above-described constitution are disposed inthem, respectively, insulation between these wiring layers (between twoadjacent wires in the wiring patterns) can be maintained by a distancebetween these connection holes. Since a large connection area can :besecured at a connection site (that is, exposed surface of the body to bewired from the bottom of the connection hole) between the body to bewired and the wiring layer owing to the constitution of the wiring layerwidening toward the body to be wired, the connection between the wiringlayer and the body to be wired can be secured sufficiently even if thereoccurs misalignment between them during the patterning of the wiringlayer.

The wiring layer includes a portion whose cross-sectional area widenstoward the body to be wired and at the same time, a space region(concave portion) in which the inner wall of the connection hole and thewiring layer are not in contact is defined therebetween, in other words,a region not in contact with the wiring layer is defined from theopening end of the inner wall of the connection hole to the bottom sidethereof so that the volume of the wiring layer corresponding to thisvoid region can be reduced. This enables thinning of the entire wiringstructure, which leads to a reduction in the amount of wire. As aresult, it is possible to reduce the wire resistance and parasiticcapacitance.

Moreover, since a void is defined between the inner wall of theconnection hole and the wiring layer, the width of the wiring layer canbe made not greater than the size of the connection hole. As a result,the width of the wiring layer can be controlled with a narrow allowanceand the amount of wire can be reduced further, making it possible toreduce the wire resistance and parasitic capacitance of the entirewiring structure further. In addition, a void appears at least in thevicinity of the opening end portion in the connection hole duringmanufacturing of the wiring structure so that conductive foreign matterswhich may be mixed in near the wiring layer can be captured by this voidand short-circuit between wiring layers which will otherwise be causedby them can be prevented.

In short, the wiring structure according to the present invention isequipped with an insulating layer having a connection hole formedtherein, a body to be wired that is placed to expose at least a portionthereof from the bottom of the connection hole, and a wiring layerconnected to the body to be wired inside the connection hole. The wiringlayer is, in other words, disposed so as to define a space region inwhich at least a portion of the inner wall of the connection hole andthe wiring layer are not in contact and which includes an opening end ofthe connection hole.

The entire portion of the wiring layer may be housed inside theconnection hole or may protrude therefrom. In other words, the uppersurface level of the wiring layer may be either lower or higher than thelevel of the opening end (open end) of the connection hole. In any case,it is preferred that the wiring layer widens toward the body to be wiredand the width (maximum width in the cross-section parallel to theopening end face) of the wiring layer at the opening end of theconnection hole is made smaller than the opening diameter (maximum widthof the connection hole at the opening end) of the connection hole.

It is more preferred that the wiring layer is disposed to cover theentire surface of the body to be wired which is exposed from the bottomof the connection hole. This makes it possible to prevent a reduction inthe wire strength or a rise in the connection resistance which willotherwise occur due to mixing of impurities in the interface between thewiring layer and body to be wired.

The printed wiring board according to the present invention ispreferably equipped with the wiring structure of the present invention.It has a plurality of wiring structures formed therein, each wiringstructure being equipped with an insulating layer having a connectionhole formed therein, a body to be wired which is disposed below orinside the insulating layer so as to expose at least a portion thereoffrom the bottom of the connection hole, and a wiring layer connected tothe body to be wired and including a portion whose cross-sectional areaincreases toward the body to be wired; and having, inside the connectionhole, a space region in which the inner wall of the connection hole andthe wiring layer are not in contact.

The method for manufacturing a wiring structure according to the presentinvention is a process for effectively fabricating the wiring structureof the present invention. It has steps of forming an insulating layer ona body to be wired, forming at least one connection hole in theinsulating layer so as to expose at least a portion of the body to bewired therefrom, and connecting the body to be wired and the wiringlayer inside the connection hole, wherein in the step of connecting thewiring layer, the wiring layer and the body to be wired are connected sothat inside the connection hole, the cross-sectional area of the wiringlayer increases toward the body to be wired and at the same time, aspace region in which the inner wall of the connection hole and thewiring layer are not in contact is defined therebetween.

The wiring structure and the like according to the present inventionmake it possible to completely connect a wiring layer and a body to bewired while maintaining insulation between two adjacent wiring layerseven if the pitch of connection holes such as via-holes is decreased. Adecrease in the pitch of connection holes contributes to the realizationof high density packaging of a printed wiring board or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are respectively a fragmentary schematic plan view andcross-sectional view illustrating one example of semiconductor-embeddedsubstrates having a preferred wiring structure according to the presentinvention;

FIG. 2 illustrates one example of a manufacturing step of asemiconductor-embedded substrate 1;

FIG. 3 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 2;

FIG. 4 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 3;

FIG. 5 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 4;

FIG. 6 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 5;

FIG. 7 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 6;

FIG. 8 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 7;

FIG. 9 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 8;

FIG. 10 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 9;

FIG. 11 illustrates one example of a manufacturing step of thesemiconductor-embedded substrate 1 following that of FIG. 10;

FIGS. 12A to 12F are cross-sectional views illustrating wiring layersaccording to other embodiments of the wiring structure of the presentinvention, respectively;

FIG. 13 illustrates manufacturing steps of another process for formingthe wiring structure of the present invention;

FIG. 14 is a perspective view illustrating the schematic structure ofthe semiconductor device; and

FIGS. 15A and 15B are a plan view and a cross-sectional viewillustrating one example of a conventional wiring structure,respectively.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will next be describedspecifically. In all the drawings, elements having like function areidentified by like reference numerals and overlapping descriptions areomitted. The positional relationship in the left-right or up-downdirection is based on the positional relationship shown in thesedrawings unless otherwise specifically indicated. The dimensional ratiois not limited to that in the drawings. The following embodiments areshown not for limiting the invention but only for explaining the presentinvention. Moreover, the present invention can be modified in variousways insofar as they do not depart from the scope of the invention.

FIG. 1A is a fragmentary schematic plan view illustrating one example ofsemiconductor-embedded substrates having one preferred wiring structureaccording to the present invention; and FIG. 1B is a cross-sectionalview taken along a line B-B of FIG. 1A.

In a semiconductor-embedded substrate 1 (printed wiring board), aconductive pattern 13 (a body to be wired) is formed on both sides of acore substrate 11 and a semiconductor device 14 is placed in a resinlayer 16 stacked over the core substrate 11. The resin layer 16 hasvia-holes 19 a and 19 b (connection holes) therein so that theconductive pattern 13 and a bump 14 p (body to be wired) of thesemiconductor device 14 placed below/above (on the side of the coresubstrate 11) and inside the resin layer 16 protrude from the resinlayer 16. Inside the via-holes 19 a and 19 b, the bump 14 p andconductive pattern 13 are connected to via-hole electrode portions 23 aand 23 b (both, wiring layers) of conductive patterns 22, respectively.

The via-hole electrode portions 23 a and 23 b include a portion having atrapezoidal cross-section as illustrated in the drawing. In other words,the substantially upper half portion of the via-hole electrode portionwidens toward the conductive pattern 13 and bump 14 p so as to increasethe cross-sectional area. They are, on both sides thereof, in contactwith the vicinity of the bottom portion on the inner wall of thevia-holes 19 a and 19 b and are not in contact thereabove, whereby aspace region (void) is defined between the inner walls of the via-holes19 a and 19 b and via-hole electrode portions 23 a and 23 b,respectively. Moreover, the via-hole electrode portions 23 a and 23 bare, at the end of the slope of the side walls thereof, brought intocontact with the side wall surfaces of the via-holes 19 a and 19 b,respectively.

The core substrate 11 serves as a base material for ensuring themechanical strength of the entirety of the semiconductor-embeddedsubstrate 1. Although no particular limitation is imposed on it, a resinsubstrate or the like can be employed. As a material of a resinsubstrate, use of a material obtained by impregnating a core materialmade of a resin cloth such as glass cloth, Kevlar fiber, aramid fiber orliquid crystalline polymer or a porous sheet of a fluorine resin in athermosetting resin or thermoplastic resin is preferred. The materialhas a thickness of preferably from about 20 μm to 200 μm. When asubstrate is subjected to laser processing, a sheet material free of acore material such as LCP, PPC, PES, PEEK or PI may be employed in orderto carry out laser processing under uniform conditions.

In this embodiment, the semiconductor device 14 is a semiconductorcomponent such as semiconductor IC (die) in the form of a bare chip.FIG. 14 is a perspective view illustrating the schematic structure ofthe semiconductor device 14. The semiconductor device 14 has many landelectrodes (not illustrated) and bumps 14 p bonded thereonto on a mainsurface 14 a having a substantially rectangular shape. In this drawing,only the bumps 14 on four corners are shown and the other bumps areomitted.

The back surface 14 b of the semiconductor device 14 has been polished,though not particularly limited, whereby the thickness t (distance fromthe main surface 14 a to the back surface 14 b) of the semiconductordevice 14 is smaller than that of a -conventional semiconductor device.The thickness is, for example, preferably 200 μm or less, morepreferably from about 10 to 100 μm. The back surface 14 b is preferablysubjected to roughening treatment by etching, plasma treatment, laserirradiation, blasting, buffing or chemical treatment in order to thinthe semiconductor device 14 further.

With regards to the polishing of the back surface 14 b of thesemiconductor device 14, it is preferred to polish a large number of thesemiconductor devices 14 simultaneously while it is in the form of awafer and then dicing the wafer into individual semiconductor devices14. When the wafer is diced into the individual semiconductor devices 14prior to thinning by polishing, the back surface 14 b can be polishedwhile covering the main surface 14 a of the semiconductor device 14 witha resin or the like.

No particular limitation is imposed on the kind of the bumps 14 p andvarious bumps such as stud bump, plate bump, plated bump and ball bumpcan be employed. In the drawing, a plate bump is illustrated as anexample.

When a stud bump is employed as the bump 14 p, a silver (Ag), copper(Cu) or gold (Au) stud bump can be formed by wire bonding. When a platebump is employed, it can be formed by plating, sputtering or vapordeposition. When a plated bump is employed, it can be formed by plating.When a ball bump is employed, it can be prepared by melting a solderball laid on a land electrode or a cream solder printed on a landelectrode. A bump obtained by curing a screen-printed conductivematerial into a conical or cylindrical shape or a bump obtained byprinting a nanopaste and sintering it by heating can also be employed.

No particular limitation is imposed on the kind of a metal usable forthe bump 14 p and examples include gold (Au), silver (Ag), copper (Cu),nickel (Ni), tin (Sn), chromium (Cr), nickel chromium alloy, and solder.Of these, copper is preferred. When the bump 14 p is made of copper, abonding strength to the land electrode can be raised compared with thatmade of gold and a higher bonding strength leads to improvement in thereliability of the semiconductor device 14.

The size and shape of the bump 14 p can be determined as neededdepending on the distance (pitch) between land electrodes. When thepitch between land electrodes is about 100 μm, the bump 14 p may beadjusted to have a maximum diameter from about 10 to 90 μm and heightfrom about 2 to 100 μm. The bumps 14 can be bonded to land electrodes byusing a wire bonder after the wafer is diced into individualsemiconductor devices 14.

The resin layer 16 is an insulating layer for electrically insulatingthe conductive pattern 13 and semiconductor device 14 from the outside.Examples of materials used for it include single substances such asvinyl benzyl resin, polyvinyl benzyl ether compound resin, bismaleimidetriazine resin (BT resin), polyphenylene ether (polyphenylene etheroxide) resin (PPE, PPO), cyanate ester resin, epoxy+active ester curedresin, polyphenylene ether resin (polyphenylene oxide resin), curablepolyolefin resin, benzocyclobutene resin, polyimide resin, aromaticpolyester resin, aromatic liquid-crystalline polyester resin,polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin,polyether ether ketone resin, fluorine resin, epoxy resin, phenol resinand benzoxazine resin; materials added, to these resins, silica, talc,calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesiumhydroxide, aluminum borate whisker, potassium titanate fibers, alumina,glass flakes, glass fibers, tantalum nitride or aluminum nitride;materials obtained by adding, to these resins, a metal oxide powdercontaining at least one metal selected from the group consisting ofmagnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin,neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium andtantalum; materials obtained by incorporating, in these resins, glassfibers or resin fibers such as glass fibers; and materials obtained byimpregnating a glass cloth, aramid fibers, nonwoven fabric or the likein these resins. From them, a proper one can be selected as needed fromthe viewpoints of electrical properties, mechanical properties, waterabsorption and reflow resistance. Although no limitation is imposed onthe thickness of the resin layer 16, it is usually from about 10 to 100μm.

The via-holes 19 a and 19 b are connection holes formed in the resinlayer 16 in order to physically connect a body to be wired such asconductive pattern 13 or semiconductor device 14 to the conductivepattern 22 and their position and depth are enough for permittingexposure of at least a portion of the conductive pattern 13 or the bump14 p of the semiconductor device 14 from the resin layer 16. In otherwords, the conductive pattern 13 and bump 14 are placed so as to exposeat least a portion of them from the bottom of the via-holes 19 a and 19b.

Although no limitation is imposed on the forming method of the via-holes19 a and 19 b, known methods such as laser processing, etching andblasting can be employed. Laser processing is accompanied withgeneration of smear. The desmear process is therefore preferablyconducted after formation of the connection hole.

The via-holes 19 a and 19 b may have any shape or size insofar as theyenable physical connection between the conductive pattern 13 and bump 14p and the via-hole electrode portions 23 a and 23 b inside thevia-holes. They can be determined as needed after due consideration oftheir depth or intended packaging density and connection stability. Theyare, for example, circular cylindrical holes having a diameter, at anopening end thereof, from about 5 to 200 μm or square cylindrical oneshaving a maximum diameter from 5 to 200 μm. They are not required to bea straight cylindrical hole. In the drawing, via-holes with an invertedpyramid shape are shown by way of example. Such via-holes 19 a and 19 bhaving a gradually increased diameter from the bottom portion toward theopening end can be obtained by boring by etching or blasting.

The conductive pattern 22 is a wiring layer electrically connected to abody to be wired such as the conductive pattern 13 or bump 14. Noparticular limitation is imposed on the material of the conductivepattern 22 and conductors ordinarily employed for wire such as metal canbe employed. The material of the conductive pattern 22 may be the sameas or different from the material used for the formation of theconductive pattern 13 or bump 14 p. When the formation process of theconductive pattern 22 includes an etching step, an etchant (etchingsolution in wet etching or etchant particles in dry etching) is selectedas needed from materials which do not etch the material of theconductive pattern 13 or bump 14 p.

Although no particular limitation is imposed on the thickness of theconductive pattern 22, it is typically from about 5 to 70 μm because anexcessively small thickness leads to deterioration in connectionstability. The thickness of the conductive pattern 22 is preferably madesmaller than the depth of the via-hole 19 a or 19 b as in thisEmbodiment because if so, the conductive patterns 22 (via-hole electrodeportions 23 a and 23 b) are housed inside the via-holes 19 a and 19 b atthe via-hole connection portions so that the wire height decreases. Thiscontributes to not only thinning but also reduction in the amount ofwire, thereby reducing the wire resistance and parasitic capacitance andmoreover, enhancing connection stability.

One example of manufacturing processes of the semiconductor-embeddedsubstrate 1 will next be explained referring to some drawings. FIGS. 2to 11 illustrate one example of manufacturing steps of asemiconductor-embedded substrate 1.

First, a resin substrate obtained by attaching a copper foil 12 to bothsides of a core substrate 11 is prepared (FIG. 2). The copper foil 12 isused for the formation of a conductive pattern 13 and use of anelectrolyte copper foil (a copper foil obtained by continuouslyelectrodepositing ionized copper in an aqueous solution of coppersulfate while using an electrodeposition roll) or rolled copper foilprepared for a printed wiring board makes it possible to reducefluctuations of the thickness as small as possible. The thickness of thecopper foil 12 can also be adjusted by sweeping or the like as needed.

The conductive pattern 13 is formed on the core substrate 11 byselectively removing the copper foil 12 attached to both sides of thecore substrate 11 by photolithography and etching (FIG. 3). At thistime, a region in which the semiconductor device 14 is to be loaded issecured by removing the copper foil 12 completely from a predeterminedregion on the core substrate 11.

Next, the semiconductor device 14 is laid in the predetermined region onthe core substrate 11 in a so-called face up position (FIG. 4). It ispreferred to temporarily fix the semiconductor device 14 onto the coresubstrate 11 with an adhesive or the like.

A resin sheet 15 having, on one side thereof, a copper foil is attachedto both sides of the core substrate 11 having the semiconductor device14 placed thereon (FIG. 5). The resin sheet 15 having, on one sidethereof, a copper foil, which is used in this manufacturing example, isobtained by attaching a copper foil 17 attached on one side of athermosetting resin sheet 16 made of a B-stage epoxy resin or the like.After such a resin sheet 15 having, on one side thereof, a copper foilis prepared and the resin surface of the sheet is attached to each ofboth sides of the core substrate 11, the resin sheet 15 and coresubstrate 11 are integrated together by hot pressing, whereby thesemiconductor device 14 is embedded in the printed wiring board and thethermosetting resin sheet 16 becomes a resin layer 16 (insulating layerformation step).

The copper foil 17 on the surface of the resin layer 16 is thenselectively removed by conformal processing to form mask patterns forthe formation of via-holes 19 a and 19 b (FIG. 6). For accomplishinghigh precision microfabrication, it is preferred to carry out conformalprocessing while utilizing photolithography and etching. Although noparticular limitation is imposed on the opening diameter of the maskpattern, that from about 10 to 200 μm is preferred and the openingdiameter is preferably increased, depending on the depth of thevia-holes 19 a and 19 b. In this step, an opening pattern 18 a is formedjust above the bump 14 p of the semiconductor device 14, while anopening pattern 18 b is formed just above the conductive pattern 13formed on the surface of the core substrate 11.

Via-holes 19 a and 19 b are then formed by sand blasting with the copperfoil 17 subjected to conformal processing as a mask (FIG. 7). In thissand blasting, blast particles such as non-metal particles or metalparticles are injected for grinding. Via-holes different in depth can beformed respectively by disposing metal layers such as bump 14 p andconductive pattern 13 just below the opening patterns 18 a and 18 b. Thebump 14 p functioning as a stopper in the formation of the via-hole 19 acan prevent the semiconductor device 14 from being damaged by the blastparticles, while the inner conductive pattern 13 functioning as astopper in the formation of the via-hole 19 b can prevent the via-hole19 b being etched further. Thus, the via-holes 19 a and 19 b are blindones and the bump 14 p and conductive pattern 13 are exposed from thebottom of the via-holes 19 a and 19 b, respectively (connection holeformation step).

An underlying conductive layer 20 is formed over almost the entireexposed surface in the via-holes 19 a and 19 b including the inner wallsurface of the via-holes 19 a and 19 (FIG. 8). The underlying conductivelayer 20 is formed preferably by electroless plating (chemical plating),but sputtering, vapor deposition or the like method can also beemployed. The underlying conductive layer 20 plays a role as anunderlying metal (or seed layer) for electrolytic plating(electroplating) which will be performed later. It is not required to bethick and for example, its thickness is selected as needed from a rangeof from several tens of nm to several μm. Electrolytic plating is thenperformed to grow a conductor metal from the underlying conductive layer20 (FIG. 9), whereby a conductive layer 21 including the underlyingconductive layer 20 is formed on the inner wall surfaces of thevia-holes 19 a and 19 b.

Resist layers 24 a and 24 b are then formed by photolithography overregions of the conductive layer 21 which will be conductive patterns 22(FIG. 10). In order to form via-hole electrode portions 23 a and 23 b ofthe conductive pattern 22 so as not to bring them into contact with theinner walls of the via-holes 19 a and 19 b, these resist layers 24 a and24 b are formed so that the widths of the resist layers 24 a and 24 b inthe via-holes 19 a and 19 b will be smaller than the upper openingdiameters ra and rb of the via-holes.

With the resist layers 24 a and 24 b as an etching mask, the conductivelayer 21 is selectively removed from a region other than the wiringpattern portions by etching to form conductive patterns 22 (via-holeelectrode portions 23 a and 23 b) (FIG. 11: wiring layer connectionstep). The etching rate of the conductive layer 21 in the vicinity ofthe mask becomes smaller than that of the other region so that the upperportions of the via-hole electrode portions 23 a and 23 b which arewiring layers thus formed each becomes wider than the lower portions.

The resist layers 24 a and 24 b on the conductive patterns 22 areremoved by a stripping solution, whereby the semiconductor-embeddedsubstrate 1 having the constitution as shown in FIG. 1 is obtained.

According to the semiconductor-embedded substrate 1 of the presentinvention equipped with such a wiring structure, the via-hole electrodeportions 23 a and 23 b include portions whose cross-sectional areaincreases gradually toward the conductive pattern 13 and bump 14 pinside the via-holes 19 a and 19 b and space regions in which the innerwalls of the via-holes 19 a and 19 b and the via-hole electrode portions23 a and 23 b are not in contact, respectively, are defined so thatinsulation between two adjacent via-holes 19 a and 19 a or insulationbetween two adjacent via-holes 19 a and 19 b can be maintained due to adistance therebetween. Accordingly, complete connection between theconductive pattern 13 and the via-hole electrode portion 23 b and thebump 14 p and the via-hole electrode portion 23 a can be ensured whilemaintaining the insulation between the two adjacent via-holes 19 a and19 a and two adjacent via-holes 19 a and 19 b. This enables high densitypackaging of the semiconductor-embedded substrate 1 due to decrease inthe pitch of the via-holes 19 a and 19 a or 19 a and 19 b.

In addition, since the via-hole electrode portions 23 a and 23 b arewider in the upper portion than in the lower portion, a large connectionarea can be secured at a connection site between the conductive pattern13 and via-hole electrode portion 23 b or between the bump 14 p and thevia-hole electrode portion 23 a (exposed surface of the conductivepattern 13 and bump 14 p from the bottom of the via-holes 19 b and 19a), via-hole electrode portions 23 a and 23 b and bump 14 p andconductive pattern 13 can be connected respectively with a sufficientarea even if misalignment occurs among them in the patterning of thevia-hole electrode portions 23 a and 23 b. This makes it possible tosecure a sufficient connection strength between the via-hole electrodeportions 23 a and 23 b and bump 14 p and conductive pattern 13,respectively, thereby preventing disconnection or a rise in theconnection resistance and improving the reliability and productivity ofthe product.

Moreover, the via-hole electrode portions 23 a and 23 b include portionswhose cross-sectional areas increase toward the bump 14 p and conductivepattern 13, respectively, and space regions (concave portions) in whichthe inner walls of the via-holes 19 a and 19 b and via-hole electrodeportions 23 a and 23 b are not in contact are defined between them sothat a volume of the wiring layer corresponding to this void decreases,leading to thinning of the entire wiring structure. In addition, owingto such a decrease in the amount of wire, the wire resistance andparasitic capacitance can be reduced.

Furthermore, a void is defined between the inner walls of the via-holeelectrode portions 23 a and 23 b and bump 14 p and conductive pattern13, respectively, so that the width of the via-hole electrode portions23 a and 23 b can be made not greater than the size of the via-holes 19a and 19 b. This makes it possible to control the width of the via-holes19 a and 19 b at a narrow tolerance and at the same time, the wireresistance and parasitic capacitance of the entire wiring structure canbe reduced further owing to a further reduction in the amount of wire. Avoid appears at least in the vicinity of the opening end portion in thevia-holes 19 a and 19 b during manufacturing of the wiring structure sothat conductive foreign matters mixed, if any, in near the via-holeelectrode portions 23 a and 23 b can be captured by this void, wherebyshort-circuit between the via-hole electrode portions 23 a and 23 b dueto foreign matters can be prevented.

Owing to the void defined between the inner walls of the via-holeelectrode portions 23 a and 23 b and bump 14 p and conductive pattern13, respectively, adhesion between the insulating layer 16 and anothermaterial stacked over the insulating layer 16 by a build-up process orsolder resist can be enhanced by an anchor effect of the void.

Other formation examples of the via-hole electrode portion 23 a havingsuch a form are illustrated in FIGS. 12A to 12F. FIGS. 12A to 12E arecross-sectional views illustrating embodiments in which the via-holeelectrode portion 23 a is, on both sides of the cross-section in thewidth direction thereof, not in contact with the inner wall of theconnection hole and thus defines a void. FIG. 12(F) is a cross-sectionalview illustrating an embodiment in which a via-hole electrode portion 23a is, on one side of the cross-section in the width direction thereof,not in contact with the inner wall of the connection hole and thusdefines a void.

The via-hole electrode portions 23 a and 23 b are disposed so as tocover therewith almost the entire exposed surface of the bump 14 p andthe conductive pattern 13 from the bottom of the via-holes 19 a and 19 bso that penetration of an etchant used for the formation of the via-holeelectrode portions 23 a and 23 b and other impurities into theconnection interface between the via-hole electrode portions 23 a and 23b and bump 14 and conductive pattern 13 can be prevented effectively andsufficient wire strength can be secured. This makes it possible toheighten the reliability of electrical connection and at the same timereduce the connection resistance at the via-hole connection portion. Inthe embodiment shown in FIG. 12B, the inner walls of the via-holes 19 aand 19 b in the vicinity of the bottom are in contact with the via-holeelectrodes 23 a and 23 b over the whole circumference so that the entireexposed surfaces of the bump 14 and conductive pattern 13 are coveredwith them more effectively. Not only the bump 14 and conductive pattern13 but also side walls of the via-holes 19 a and 19 b are covered withthe via-hole electrode portions 23 a and 23 b so that corrosion of aconductor due to penetration of water or the like from above, if any,can be prevented.

It was presumed that when the opening end portion of a connection holeis not covered completely with a wiring layer, deterioration in thereliability of electrical connection or increase in the resistance atthe connection portion may occur. In order to completely cover theopening end portion of a connection hole to prevent occurrence of themeven if there occurs misalignment between the connection hole and awiring layer to be formed, there is a tendency to employ a patterndesign of making the width of the wiring layer greater than the diameterof the connection hole.

According to the finding of the present inventors, not a covering ratioof the opening end portion of the connection hole but a covering ratioof the surface of a body to be wired which is exposed from the bottomwall of the connection hole has an influence on the reliability ofelectrical connection or resistance at the via-hole connection portion.

The entire exposed surface of the body to be wired can be covered withthe wiring layer by, when the wiring layer is formed by the subtractiveprocess as described in the above-described manufacturing example,adjusting etching conditions at the time when the conductive layer 21other than the wiring pattern portion is selectively removed by etching(FIG. 11) and terminating etching before etching for the removal of theconductive layer 21 reaches the conductive pattern 13 and bump 14 p.Even if there occurs misalignment in the position of the wiring layerthus formed, the entire exposed surface of the body to be wired can becovered by the wiring layer by determining the etching conditions suchas etching amount as needed in consideration of the expectedmisalignment.

When the wiring structure is formed by the additive process as shownlater in FIG. 13, it is recommended to make the opening widths ma and mbof a mask layer 132, which is formed in portions other than wiringpatterns (FIG. 13B), greater than the diameters r′_(130a) and r′_(130b)(diameters of the bottom walls of the via-holes) of the exposed surfacesof the bodies to be wired. It is also recommended to determine theopening widths ma and mb of the mask layer 132 to be greater than thediameters r′_(130a) and r′_(130b) of the exposed surfaces of the bodiesto be wired so as to allow a margin for the expected misalignment,whereby the entire exposed surface of the body to be wired can becovered with the wiring layer even if there occurs misalignment in theposition where the wiring layer is formed.

One example of manufacturing processes using an additive process (aprocess of selectively forming a wiring layer in a wiring patternportion) will next be described referring to some drawings, as anotherexample of manufacturing a wiring structure according to the presentinvention. FIG. 13A to FIG. 13D illustrate another example of thefabrication steps of the wiring structure of the present invention.

A multilayer printed wiring board having an insulating layer 131 inwhich connection holes 130 a and 130 b have been formed to exposeportions of the upper surface of an internal wiring layer which is abody to be wired is prepared (FIG. 13A).

A mask layer 132 made of a photoresist is then formed over portionsother than wiring patterns (FIG. 13B). In order to avoid contact of theboth side surfaces of a wiring layer with the upper inner walls of theconnection holes, opening widths ma and mb of the mask layer 132 aremade smaller than the upper opening diameters r′_(130a) and r′_(130b) ofthe connection holes 130 a and 130 b. After formation of wiring layers133 a and 133 b by electroless plating (FIG. 13C), the mask layer 132over the wiring patterns is removed by using a stripping solution,whereby wiring layers 133 a and 133 b are formed so as to define a voidincluding an opening end of the connection hole between the both innerwalls of the connection hole (FIG. 13D: wiring layer connection step).

The semiconductor-embedded substrate having a wiring structure obtainedin such a manner exhibits similar advantages to those available by thesemiconductor-embedded substrate 1 illustrated in FIG. 1.

As described above, the present invention is not limited to theabove-described embodiments but can be modified in various ways withoutchanging the scope of the invention. For example, the wiring structureof the present invention is not limited to a single layer structurehaving a wiring layer as the uppermost layer but can be applied to amultilayer structure fabricated by a known buildup technologyconventionally employed for the manufacture of a multilayer printedwiring board. In this case, a void defined between the via-holes 19 aand 19 b and via-hole electrode portions 23 a and 23 b, respectively, inFIG. 1 may be filled with an insulating layer formed thereover. Inaddition, the body to be wired in the present invention is not limitedto the conductive pattern 13 or bump 14 p of a semiconductor device butit embraces all the bodies to be wired such as electrodes of electroniccomponents such as resistor and capacitor to be connected to a wiringlayer.

Moreover, in the wiring structure of the present invention, thepositional relationship between the body to be wired be connected to thewiring layer and another component is not limited to those present ondifferent planes in the same resin layer 16. Alternatively, they may beplaced on the same plane or different planes in the same layer or may beplaced on different layers.

The conductive pattern 22 which is a wiring layer is required not to bein contact with at least a portion of the inner wall of the via-holes 19a and 19 b communicated with the upper surface of the resin layer 16.They may be not in contact with the inner wall only on the widthwise oneside of the wiring layer, which means that a void is formed only on oneside of the wiring layer. From the viewpoint of maintaining insulation,however, the wiring layer is desirably not in contact with the innerwall of the connection hole on the widthwise both sides of the wiringlayer.

The cross-sectional shape of the via-hole electrode portions 23 a and 23b is not limited to a hexagonal shape as illustrated in the drawings,but they may widen toward the body to be wired without stopping thewidening on their way so as to increase their cross-sectional area. Theyhave any shape insofar as they define a space including opening ends ofthe via-holes 19 a and 19 b between the inner walls of the via-holes 19a and 19 b and side walls of the via-hole electrode portions 23 a and 23b (refer to the above FIGS. 12A to 12F). In addition, the upper surfaceof the via-hole electrode portions 23 a and 23 b is not limited to aflat shape but may have, for example, convex portions or concaveportions, or may be steepled. The upper surface is not limited to beparallel to the substrate surface, but may be, for example, inclined.

In the above-described manufacturing example, the wiring layer is formedso as to define a void at the upper portion of the inner walls of thevia-holes 19 a and 19 b which are connection holes by adjusting thewidth of the resist layers 24 a and 24 b in the wiring layer formationstep. Alternatively, a wiring layer once formed may be subjected to postprocess, for example, exposure to laser in order to trim a contactportion between the wiring layer and inner wall of the connection hole.From the viewpoint of simplifying the manufacturing steps, it is desirednot to add a post process but to directly form a wiring layer not incontact with at least a portion of the inner wall of the connectionhole. In the above-described manufacturing example, a subtractiveprocess or additive process is used for the formation of a wiring layer,but a semi-additive process can also be employed.

As described above, according to the wiring structure, manufacturingmethod of the same and printed wiring board of the present invention, itis possible to connect a wiring layer to a body to be wired completelywhile keeping insulation between two adjacent wiring layers and therebyrealize high density packaging due to decrease in pitch. They cantherefore be applied widely and effectively to apparatuses, equipment,systems and various devices equipped therein with active components suchas semiconductor devices and/or passive components such as resistor andcapacitor, particularly, those which need miniaturization andperformance enhancement.

1. A wiring structure comprising: an insulating layer having aconnection hole formed therein; a body to be wired that is placed so asto expose at least a portion thereof from the bottom of the connectionhole, and a wiring layer connected to the body to be wired inside theconnection hole, wherein the wiring layer has a portion whosecross-sectional area increases toward the body to be wired and isdisposed so as to define a space region in which at least a portion ofthe inner wall of the connection hole and the wiring layer are not incontact.
 2. The wiring structure according to claim 1, wherein a widthof the upper portion of the wiring layer is made smaller than an openingdiameter of the connection hole.
 3. The wiring structure according toclaim 1, wherein the wiring layer is disposed so as to cover the entireexposed surface of the body to be wired that is exposed from the bottomof the connection hole.
 4. A printed wiring board comprising a pluralityof wiring structures formed therein, the wiring structures eachcomprising an insulating layer having a connection hole therein, a bodyto be wired that is placed below or inside the insulating layer so as toexpose at least a portion from the bottom of the connection hole, and awiring layer which is connected to the body to be wired inside theconnection hole and includes a portion whose cross-sectional areaincreases toward the body to be wired; and having a space region, inwhich the inner wall of the connection hole and the wiring layer are notin contact, defined inside the connection hole.
 5. A method formanufacturing a wiring structure, which comprises: an insulating layerformation step for forming an insulating layer on a body to be wired, aconnection hole formation step for forming at least one connection holein the insulating layer so as to expose at least a portion of the bodyto be wired from the connection hole, and a wiring layer connection stepfor connecting the wiring layer to the body to be wired inside theconnection hole, wherein in the wiring layer connection step, the wiringlayer is connected to the body to be wired so as to include a portionwhose cross-sectional area increases toward the body to be wired insidethe connection hole and to define a space region in which the inner wallof the connection hole is not in contact with the wiring layer.
 6. Thewiring structure according to claim 2, wherein the wiring layer isdisposed so as to cover the entire exposed surface of the body to bewired that is exposed from the bottom of the connection hole.